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1And in Conclusion\dots

Our goal this lecture was to build combinational logic blocks. We can summarize this approach with the following diagram:

"TODO"

Figure 1 in previous section.

We discussed how to convert among these three representations, as represented by the arcs in the diagram. Here is a summary:

In digital electronics, it is often important to get certain outputs based on your inputs, as laid out by a truth table. Truth tables map directly to Boolean expressions, and Boolean expressions map directly to logic gates. However, in order to minimize the number of logic gates needed to implement a circuit, it is often useful to simplify long Boolean expressions.

We can simplify expressions using the nine key laws of Boolean algebra:

AND FormOR Form
xy=yxx \cdot y = y \cdot xx+y=y+xx + y = y + xCommutativity
(xy)z=x(yz)(xy)z = x(yz)(x+y)+z=x+(y+z)(x + y) + z = x + (y + z)Associativity
x1=xx \cdot 1 = xx+0=xx + 0 = xIdentity
x0=0x \cdot 0 = 0x+1=1x + 1 = 1Laws of 0’s and 1’s
xy+x=xxy + x = x(x+y)x=x(x + y)x = xUniting Theorem
x(y+z)=xy+xzx(y + z) = xy + xzx+yz=(x+y)(x+z)x + yz = (x + y)(x + z)Distributivity
xx=xx \cdot x = xx+x=xx + x = xIdempotence
xx=0x \cdot \overline{x} = 0x+x=1x + \overline{x} = 1Inverse (Complement)
xy=x+y\overline{xy} = \overline{x} + \overline{y}x+y=xy\overline{x + y} = \overline{x} \cdot \overline{y}DeMorgan’s Laws

Laws of Boolean Algebra (reprint of Table 3 from this section).

Additionally, we have many boolean functions which take boolean signals (0 or 1) as input and output a boolean result (0 or 1). When designing digital systems, boolean functions are represented as logic gates. Common logic gates can be found in this section

There are two basic types of circuits: combinational logic circuits and state elements. Combinational logic circuits simply change based on their inputs after whatever propagation delay is associated with them. For example, if an AND gate (pictured below) has an associated propagation delay of 2ps, its output will change based on its input as follows:

"TODO"

You should notice that the output of this AND gate always changes 2ps after its inputs change. State elements, on the other hand, can remember their inputs even after the inputs change. State elements change value based on a clock signal. A rising edge-triggered register, for example, samples its input at the rising edge of the clock (when the clock signal goes from 0 to 1).

2Textbook Readings

P&H A.3-A.6

3Additional References

These notes would not be possible without Professor John Wawrzynek’s CS 61C handouts:

4Exercises

Check your knowledge!

4.1Conceptual Review

  1. True/False: Simplifying boolean logic expressions will not affect the performance of the hardware implementation.

  1. True/False: The fewer logic gates, the faster the circuit (assuming each gate has the same propagation delays).

  1. True/False: The time it takes for clock-to-q and register setup can be greater than one clock cycle.

  1. True/False: Every possible combinational logic circuit can be expressed by some combination of NOR gates.

  1. True/False: The shortest combinational logic path between two state elements is useful in determining circuit frequency and minimum clock cycle.

4.2Short Exercises

  1. Label each of the following logic gates with their respective boolean function, and draw a truth table representing their outputs:

"TODO"